Approx_mult_completed

cme433_lrtestbench-main/src/Ei_find.sv

 module Ei_find (
     input [3:0] S,
     input  logic signed [ 7:0] i_a,
-    output reg [3:0] E
+    output reg [3:0] E,
+    input [2:0] group[0:3]
 );
 
 always @ *
     begin
     integer i;
     for (i=0; i<4; i= i+1)
-        E[i] = ~(S[i] ^ i_a[7]);
+        if (group[i] == 3'b0 || group[i] == 3'b111)
+            E[i] = 1'b1;
+        else
+            E[i] = ~(S[i] ^ i_a[7]);
     end
 
 endmodule
\ No newline at end of file

cme433_lrtestbench-main/src/Si_find.sv

@@ -8,7 +8,7 @@ reg [8:0] group_select_binary;
 
 // radix-4 recoding
 always @ *
-  group_select_binary[8:1] = i_b;
+  group_select_binary = {i_b, 1'b0};
 
 always @ *
   begin
@@ -21,7 +21,11 @@ always @ *
         //   default: S[i] = 1'b0;
         // endcase
 
-        S[i] = group_select_binary[2];
+        if (group_select_binary[2:0] == 3'b000 || group_select_binary[2:0] == 3'b111)
+          S[i] = 1'b0;
+        else
+          S[i] = group_select_binary[2];
+          
         group[i] = group_select_binary[2:0];
         group_select_binary = group_select_binary >> 2;
       end

cme433_lrtestbench-main/src/approx_mult.sv

@@ -4,19 +4,13 @@ module approx_mult (
     output logic signed [15:0] o_z
 );
 
-always @ *
-  begin
-
-    $display("\nA: %d, B: %d", i_a, i_b);
-    $display("A: %b, B: %b", i_a, i_b);
-    $display("A[7]: %b", i_a[7]);
-    $display("S: %b, E: %b\n", S, E);
-
-  end
 
 reg [3:0] S;
 reg [3:0] E;
 
+reg [8:0] pp0,pp1,pp2,pp3;
+
+
 reg [11:0] partial_product_0;
 reg [10:0] partial_product_1, partial_product_2;
 reg [9:0] partial_product_3;
@@ -27,26 +21,78 @@ reg [2:0] group[0:3];
 Ei_find e(
   .S(S),
   .i_a(i_a),
-  .E(E)
+  .E(E),
+  .group(group)
 );
 
+// always @ *
+//   begin
+//     $display("nam E[0] = %b", E[0]);
+//     $display("nam E[1] = %b", E[1]);
+//     $display("nam E[2] = %b", E[2]);
+//     $display("nam E[3] = %b", E[3]);
+//   end
+
+// stage 2
 Si_find s(
   .i_b(i_b),
   .S(S),
   .group(group)
 );
 
-// result r(
-//   .partial_product_0(partial_product_0),
-//   .partial_product_1(partial_product_1),
-//   .partial_product_2(partial_product_2),
-//   .partial_product_3(partial_product_3),
-//   .result(result)
-// )
+// always @ *
+//   begin
+//     $display("nam group[0] = %b", group[0]);
+//     $display("nam group[1] = %b", group[1]);
+//     $display("nam group[2] = %b", group[2]);
+//     $display("nam group[3] = %b", group[3]);
+
+//     $display("nam S[0] = %b", S[0]);
+//     $display("nam S[1] = %b", S[1]);
+//     $display("nam S[2] = %b", S[2]);
+//     $display("nam S[3] = %b", S[3]);
+//   end
 
-// stage 2
 // stage 3
+partial_product pp_0(.i_a(i_a), .radix_option(group[0]), .partial_p(pp0));
+partial_product pp_1(.i_a(i_a), .radix_option(group[1]), .partial_p(pp1));
+partial_product pp_2(.i_a(i_a), .radix_option(group[2]), .partial_p(pp2));
+partial_product pp_3(.i_a(i_a), .radix_option(group[3]), .partial_p(pp3));
+
+// always @ *
+//   begin
+//     $display("nam pp0 = %b", pp0);
+//     $display("nam pp1 = %b", pp1);
+//     $display("nam pp2 = %b", pp2);
+//     $display("nam pp3 = %b", pp3);
+//   end
 
 // stage 4
+approx_model approx1(
+ .pp0(pp0), .pp1(pp1), .pp2(pp2), .pp3(pp3),
+ .E(E),
+ .pp0_out(partial_product_0),
+ .pp1_out(partial_product_1),
+ .pp2_out(partial_product_2),
+ .pp3_out(partial_product_3)
+);
+
+// always @ *
+//   begin
+//     $display("nam partial_product_0 = %b", partial_product_0);
+//     $display("nam partial_product_1 = %b", partial_product_1);
+//     $display("nam partial_product_2 = %b", partial_product_2);
+//     $display("nam partial_product_3 = %b", partial_product_3);
+//   end
+
 // stage 5
+final_result r(
+  .partial_product_0(partial_product_0),
+  .partial_product_1(partial_product_1),
+  .partial_product_2(partial_product_2),
+  .partial_product_3(partial_product_3),
+  .S(S),
+  .total(o_z)
+);
+
 endmodule : approx_mult

cme433_lrtestbench-main/src/final_result.sv

+module final_result(
+    input signed [11:0] partial_product_0,
+    input signed [10:0] partial_product_1, partial_product_2,
+    input signed [9:0] partial_product_3,
+    input [3:0] S,
+    output logic signed [15:0] total
+);
+
+logic signed [15:0] pp_16[0:3];
+
+logic signed [15:0] s_16[0:3];
+
+always @ *
+    begin
+        pp_16[0] = {4'b0, partial_product_0};
+        pp_16[1] = {3'b0, partial_product_1, 2'b0};
+        pp_16[2] = {1'b0, partial_product_2, 4'b0};
+        pp_16[3] = {partial_product_3, 6'b0};
+
+        s_16[0] = {15'b0, S[0]};
+        s_16[1] = {13'b0, S[1], 2'b0};
+        s_16[2] = {11'b0, S[2], 4'b0};
+        s_16[3] = {9'b0, S[3], 6'b0};
+
+        pp_16[0] = pp_16[0] + s_16[0];
+        pp_16[1] = pp_16[1] + s_16[1];
+        pp_16[2] = pp_16[2] + s_16[2];
+        pp_16[3] = pp_16[3] + s_16[3];
+
+        total =pp_16[0] +pp_16[1] +pp_16[2] +pp_16[3];
+    end
+
+// always @ *
+//     begin
+        
+
+//         $display("pp_16: %b",pp_16[0]);
+//         $display("pp_16: %b",pp_16[1]);
+//         $display("pp_16: %b",pp_16[2]);
+//         $display("pp_16: %b",pp_16[3]);
+//         $display("\npartial_product_0: %b",partial_product_0);
+//         $display("partial_product_1: %b",partial_product_1);
+//         $display("partial_product_2: %b",partial_product_2);
+//         $display("partial_product_3: %b\n",partial_product_3);
+//         $display("\nS_0: %b",S[0]);
+//         $display("S_1: %b",S[1]);
+//         $display("S_2: %b",S[2]);
+//         $display("S_3: %b\n",S[3]);
+        
+//         $display("total = %b", total);   
+// end
+
+
+
+
+
+endmodule

cme433_lrtestbench-main/src/partial_product.sv

@@ -10,9 +10,9 @@ always @ * begin
 	else if (radix_option == 3'd4)
 		partial_p = ~(2*i_a);
 	else if ((radix_option == 3'd1) || (radix_option == 3'd2))
-		partial_p = i_a;
+		partial_p = {i_a[7],i_a};
 	else if ((radix_option == 3'd5) || (radix_option == 3'd6))
-		partial_p = ~(i_a);
+		partial_p = {~i_a[7],~(i_a)};
 	else
 		partial_p = 9'd0;
 end

cme433_lrtestbench-main/src/result.sv

-module result(
-    input [11:0] partial_product_0,
-    input [10:0] partial_product_1, partial_product_2,
-    input [9:0] partial_product_3,
-    input [3:0] S,
-    output reg [15:0] result
-);
-
-reg [15:0] pp_16[0:3];
-
-always @ *
-    begin
-        pp_16[0] = pp_16[0] + partial_product_0;
-        pp_16[1] = pp_16[1] + partial_product_1;
-        pp_16[2] = pp_16[2] + partial_product_2;
-        pp_16[3] = pp_16[3] + partial_product_3;
-
-        result = pp_16[0] + pp_16[1] << 2 + (pp_16[2] + S[2]) << 4 + (pp_16[3] + S[3]) << 6;
-    end
-
-
-
-endmodule
\ No newline at end of file